Pulse train to sinusoid Converter Wiring diagram Schematic

The schema letsyou convert a serial pulse stream or sinusoidal input to a sinusoidal output at 1/32 the frequency. By varying the frequency of Vrn, you can achieve an output range ofl07:1-from about 100 kH2 to less than 0.01 H2. The output resembles that of a 5-bit d/a converter operating on paralleLdigital data. Counter IC1 generates binary codes that repeatedly scan the range from 00000 to 11111. The output amplifier adds the corresponding XOR gate outputs, Vvv or ground, weighted by the values of input resistors R1 through R4.

Pulse-train-to-sinusoid-Converter Circuit Diagram

The 16 counter codes 00000 to 01111, for instance, pass unchanged to the XOR gate outputs, and cause Vom to step through the half-sinusoidal cycle for maximum amplitude to minimum amplitude. Counter output Q4 becomes high for the next 16 codes, causing the XOR gates to invert the QO through Q3 outputs. As a result, VouT steps through the remaining half cycle from minimum to maximum amplitude. The counter then rolls over and initiates the next cycle. You can change the R1 through R4 values to obtain other VouT waveforms. VDv should be at least 12 V to assure maximum-frequency operation from IC1 to IC2.