Digital High Low Logic Tester Circuit diagram

1. 
   When the input signal is logic 1, the display shows H’ and the loudspeaker emits a note which is an octave higher than the low’ tone. Operation of the circuit can be seen from the circuit diagram in figure 1 and the truth table in figure 2. When the input signal is 1, transistor T1 conducts taking the input of gate N2 above the trigger threshold and the trigger output goes to logic 0.
2. This is not our first high and low tester, but the present circuit offers something new: a seven-segment display which shows ’H or ’L’ and at the same time a small loudspeaker emits a corresponding tone.
3. lf required, the loudspeaker can be switched on by means of S1. The switch can, of course, be omitted if the audio tone is always required. lf you have an ear for music, R10 and R12 may be replaced by a 220 Q resistor and a 2509 preset potentiometer so that the tone can be adjusted to your particular liking.!
4. And all that at very reasonable cost.
5. When the supply is switched on, the decimal point of the display lights and indicates that the unit is ready For use. lf this is not the case, or an undefined signal is applied to the input, the display, apart from the decimal point, remains dark and the loudspeaker remains silent. lf the input signal is logic O, the display shows ’L’ and the loudspeaker emits a low note.
6. When the input signal is logic 0, T1 is cut off and T2 conducts. The voltage at the inputs of gates N1 and N2 are below the trigger threshold and both outputs are logic 1, switching on transistors T3 and T4; the emitter voltage of T4 rises and cuts off diodes D4 and D5. This causes a current to flow through segments d, e and f, diodes D2 and D3, resistor R6 and transistor T3.
7. With non-defined inputs (between 0.8.. . 2.15 V) and an open circuit input, both input transistors are cut off, The output of N1 is then logic 0 and that of N2 is logic 1: no current can therefore flow through any of the segments. As regards the drive for the two oscillators, suffice it to say that during low inputs N3 is driven by the output of N1 and during high in- puts N4 is driven directly by T1.
8. Transistor T2 (PNP!) is cut off, the input of gate N1 is also above the trigger threshold and this trigger output is therefore also logic 0. Both switching transistors T3 and T4 are off and a current flows through the corresponding segments (b, c, e, f, g), diodes D4 and D5 and R7.